A New Method for the High-Level Synthesis of Continuous-Time Cascaded Σ∆ Modulators
نویسندگان
چکیده
ABSTRACT This paper presents an efficient method to design cascaded Σ∆ modulators implemented with continuous-time circuits. Instead of using a discrete-to-continuous time transformation, the proposed methodology is based on the direct synthesis of the whole cascaded architecture. This leads to more efficient topologies in terms of circuit complexity, power consumption and robustness with respect to parasitics. As an application, new cascaded topologies are synthesized and optimized to cope with VDSL specifications.(*)
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